The transmission of digital data between subsystems in an overall system in which the various subsystems are required to interact can present difficult interfacing problems. For example, in military aircraft systems the data bus will typically be used for communications between various subsystems manufactured by different vendors. In the absence of a defined communications protocol the different vendors would be free to choose any attractive standard established in the market place. In order to promote uniformity among its different vendors, the government promulgated a military standard, officially known as AIRCRAFT INTERNAL TIME DIVISION COMMAND/RESPONSE MULTIPLEX DATA BUS, MIL-STD-1553B to define the requirements for data bus techniques which are to be utilized in systems integration of military aircraft subsystems.
It is possible to devise interface circuitry that permits a vendor to interface with a MIL-STD-1553B bus without imposing excessive overhead on the subsystem itself. For example, U.S. Pat. No. 4,136,400, granted to Caswell et al., granted on Jan. 23, 1979 assigned to Rockwell International Corporation, discloses a micro-programmable data terminal for use as in an interface circuit in a MIL-STD-1555B system. The Caswell circuitry is usable as either as a bus controller or a terminal. (A remote terminal is a circuit that simply provides the interface between the bus and a subsystem. A bus controller is a circuit that serves the function of issuing instructions to the other subsystems and monitoring the bus to prevent improper communications.) A disadvantage of the Caswell device is that it is not capable of interfacing with a redundant bus. It is also disadvantageous in situations in which the bus controller function is not required. Moreover, the Caswell device achieves only limited functional capability with the hardware employed.
Other manufacturers have disclosed architectures which perform the complete MIL-STD-1553B protocol function. For example, Circuit Technology Inc. (CTI) of Farmingdale, N.Y. has disclosed a circuit that uses five LSI chips to perform remote terminal, passive monitor or bus controller functions for a dual redundant system. However, the CTI device requires a large number of logic gates to achieve a limited functional capability. The chip's capabilities are limited to message verification, word count, status word generation, storage of current and last commands, the broadcast option, and mode code handling.
An architecture which reduces the number of logic gates required to achieve a high degree of functionality while at the same time relieving the host subsystem overhead to a very large degree is needed.